The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks and logic elements and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic(trademark), MAX(copyright) 5000, MAX(copyright) 7000, FLEX(copyright) 8000, and FLEX(copyright) 10K families of devices made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the logic array blocks. LABs contain a number of relatively elementary logic individual programmable logic elements (LEs) which provide relatively elementary logic gates such as NAND, NOR, and exclusive OR gates.
Resulting from the continued scaling and shrinking of semiconductor device geometries, which are used to form integrated circuits (also known as xe2x80x9cchipsxe2x80x9d), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks. In particular, it is important to provide enough interconnection resources between the programmable logic elements so that the capabilities of the logical elements can be fully utilized and so that complex logic functions (e.g., requiring the combination of multiple LABs and LEs) can be performed, without providing so much interconnection resources that there is a wasteful excess of this type of resource.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up more general purpose and therefore long distance interconnection resources, etc. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
As can be seen, an improved programmable logic array integrated circuit architecture is needed, especially an architecture providing additional possibilities for interconnections between the logic modules and improved techniques for organizing and interconnecting the programmable logic elements, including LABs and LEs.
The present invention is a programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. In one embodiment, the present invention implements a three-stage Clos network.
After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. Provable routability refers to a condition where it has been mathematically shown, as long as certain constraints have been satisfied, that a signal at any input at the first stage may be routed to any output at the third stage.
A LAB of the present invention comprises an input multiplexer region (IMR), logic elements, input-output pins, and output multiplexer region (OMR). The PLD of the present invention implements a Clos network in the directions of the programmable global horizontal interconnect (row) and programmable global vertical interconnect (column).
More specifically, for the row interconnect, the OMR implements a full crossbar switch for the first stage of a Clos network. Multiplexers in a programmable global horizontal interconnect form a second stage. And, the IMR implements a full crossbar switch for a third stage of a Clos network. For the column interconnect, the IMR implements a first stage of a Clos network. Multiplexers in the programmable global vertical interconnect form a second stage. And, the OMR forms a third stage of a Clos network.
In accordance with the teachings of the present invention, a logic array block for a programmable logic device is disclosed, which includes: a plurality of logic elements, where the logic elements are programmably configurable to implement logical functions; an input multiplexer region, which programmably couples a plurality of global horizontal conductors to inputs of the logic elements; and an output multiplexer region, which programmably couples outputs of the logic elements to the plurality of global horizontal conductors.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.